Staff Physical Design Engineer - SoC EMIR Engineer
To apply, save or open the job page, sign in. Sign-up is by invitation only for now, and after signing in you come straight back to this job. No invite? Ask to join
Summary
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI.
Requirements
- Bachelor's or Master's degree in Electrical Engineering or a related technical field
- 7+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products
- Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus)
- Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm)
- Deep understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture
- Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM
- Familiarity with thermal analysis tools and their interaction with electrical performance (advantage)
- Experience working with sign-off criteria and margins for high-volume production chips (advantage)
- Good understanding of timing and P&R (advantage)
- Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution (advantage)
- Ability to write TCL scripts for STA and Fusion Compiler (FC) (advantage)