Staff/ Principal Design Verification Engineer
כדי להגיש, לשמור או לפתוח את דף המשרה מתחברים עם Google. זה חינם, ואחרי ההתחברות חוזרים ישר למשרה הזו.
תקציר
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI.
דרישות
- Bachelor's degree in Electrical Engineering or related technical field
- 5+ years of proven experience in ASIC verification within the semiconductor industry
- Hands-on experience developing components within complex verification environments using SystemVerilog
- Strong working knowledge of standard verification methodologies, specifically UVM
- Sharp analytical mind with passion for debugging and technical problem-solving
- Excellent communication skills with ability to thrive in collaborative R&D environments
- Master's degree in Electrical Engineering or related field (advantage)
- Familiarity with Formal Verification or Emulation flows (advantage)
- Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks (advantage)
- Exposure to industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL (advantage)
- Experience with assertion-based verification and c (advantage)