Senior/ Staff Formal Verification Engineer

Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel · פורסמה לפני 223 ימים

כדי להגיש, לשמור או לפתוח את דף המשרה מתחברים עם Google. זה חינם, ואחרי ההתחברות חוזרים ישר למשרה הזו.

תקציר

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI.

דרישות

• Bachelor's degree in Electrical Engineering or a related technical field
• 4+ years of hands-on experience in Formal Verification within semiconductor companies
• Deep expertise in formal verification methodologies, tools, and flows
• Strong understanding of RTL design and verification principles
• Experience with industry-standard formal verification tools (Jasper, VC Formal, or similar)
• Excellent communication skills, strong analytical thinking, and a proactive, "can-do" approach to problem-solving
• Track record of successfully taking complex blocks or subsystems through the entire formal verification lifecycle (advantage)
• Experience with SystemVerilog UVM-based design verification (advantage)
• Knowledge of networking standards (Ethernet, NVLink, UALink, PCIe) (advantage)
• Background in high-speed serial interface verification (advantage)