Staff/ Principal Physical Design STA Engineer
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תקציר
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI.
דרישות
- B.Sc. in Electrical Engineering or Computer Engineering
- 6+ years of hands-on experience in Static Timing Analysis (STA) at semiconductor companies, specifically working on advanced process technologies. (Note: Adjust years of experience based on the exact level you are targeting)
- Deep expertise in multi-scenario STA, as well as timing and SDC constraint development and verification at the block and subsystem levels
- Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off
- Solid knowledge of physical design flows (Synthesis, P&R, Physical Verification) and how they intersect with timing closure
- Experience developing and validating constraints using industry-standard tools like Timing Constraints Manager (Synopsys) or TimeVision (Ausdia) (advantage)
- Proven track record of executing STA on complex Macro-level designs and supporting Full-Chip timing integration (advantage)
- Strong background in scripting (Tcl, Python, Perl) and automation to enhance timing closure efficiency (advantage)