Senior ASIC Design Engineer
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Summary
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI.
Requirements
- Bachelor's degree in Electrical Engineering or related technical field
- 3+ years of experience in logic design at semiconductor companies
- Knowledge and experience in Verilog and/or SystemVerilog
- Excellent communication skills with ability to work effectively across teams
- Understanding of digital design principles and RTL coding best practices
- Master's degree in Electrical Engineering or related field (advantage)
- Knowledge of DDR and PCIe protocols and implementation (advantage)
- Understanding of power management techniques for low-power design (advantage)
- Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis (advantage)
- Proficiency in scripting languages such as Python or Perl (advantage)
- Experience with high-speed serial interface designs or connectivity protocols (advantage)