Manager Design Verification
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תקציר
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI.
דרישות
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
- 5+ years of digital design experience, including at least one full chip from spec to tapeout
- Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows
- Hands-on experience with timing closure, CDC, lint, and low-power design techniques
- Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration
- MS or PhD in Electrical Engineering or Computer Engineering (advantage)
- Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs (advantage)
- Familiarity with formal verification, emulation, or assertion-based methodologies (advantage)
- Background in advanced process nodes (7nm, 5nm, or below) (advantage)
- Strong debug skills across pre-silicon and post-silicon environments (advantage)