Staff/ Principal Chip Top Physical Design Engineer

Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel · פורסמה לפני 223 ימים

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תקציר

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI.

דרישות

• B.Sc. or M.Sc. in Electrical Engineering
• 5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below)
• Proven experience executing complex block or chip-level projects with a proactive, "can-do" approach and excellent communication skills
• Deep hands-on expertise in RTL2GDS flows, including P&R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR
• Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus)
• Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration
• Deep understanding of Power & Noise analysis (EM/IR) (advantage)
• Experience with DFT (Design for Test) integration into the physical design flow (advantage)
• Background in high-speed interfaces or data center protocols (advantage)